1. Field of the Invention
The instant disclosure relates to a power transistor (MOSFET); in particular, to a trench power MOSFET having a shielding electrode in the bottom of the trench.
2. Description of Related Art
Power metal-oxide-semiconductor field-effect transistors (Power MOSFET) are widely implemented in the switching devices of electric devices, such as power supplies, rectifiers or low voltage motor controllers and the like. The current power MOSFET is designed to have a vertical structure to improve the packing density. One of the advantages of the trench power MOSFET is that it is capable of controlling the operation of devices with low-power consumption.
The working loss of power MOSFET is categorized into a switching loss and a conducting loss. In addition, an intrinsic gate-to-drain capacitance (Cgd) is one of the important parameters affecting the switching loss. When the intrinsic gate-to-drain capacitance is too high, the switching loss increases, which may limit the switching speed of the power trench MOSFET and may lead to the power MOSFET being unfavorable to be implemented in high frequency circuits.
To improve the abovementioned problem and decrease the gate-to-drain capacitance (Cgd), the prior art power MOSFET has a shielding electrode formed in the gate trench and positioned at a lower portion of the gate trench.
However, during the fabricating process of the trench power MOSFET having the shielding electrode, after the step of forming the shielding electrode in the lower portion of the gate trench, a portion of the dielectric layer, which has been formed along an upper portion of an inner wall of the gate trench during previous steps, has to be removed, and then another gate dielectric layer is redeposited. Notably, during the step of etching the dielectric layer, it is difficult to control a depth of the etching process, which may result in the formations of voids or holes between the redeposited gate dielectric layer and the remained dielectric layer covering along a lower portion of the inner wall of the gate trench. When a bias is applied to the trench power MOSFET, the voids or holes in the gate trench may lead to the generation of leakage current between the gate and the source and produce a problem of poor electrical performance.